Semiconductor device

ABSTRACT

An object of the present invention is providing a semiconductor device that is capable of improving the reliability of a semiconductor element and enhancing the mechanical strength without suppressing the scale of a circuit. The semiconductor device includes an integrated circuit sandwiched between first and second sealing films, an antenna electrically connected to the integrated circuit, the first sealing film sandwiched between a substrate and the integrated circuit, which includes a plurality of first insulating films and at least one second insulating film sandwiched therebetween, the second sealing film including a plurality of third insulating films and at least one fourth insulating film sandwiched therebetween. The second insulating film has lower stress than the first insulting film and the fourth insulating film has lower stress than the third insulating film. The first and third insulating films are inorganic insulating films.

TECHNICAL FIELD

The present invention relates to a semiconductor device which is capableof communicating via radio waves.

BACKGROUND ART

A semiconductor device typified by an ID chip, which can send andreceive data such as identification information by radio, has been putto practical use in various fields. The semiconductor device has beenexpected to expand a market as a new type of a communication andinformation terminal. The ID chip is also referred to as a wireless tag,RFID (radio frequency identification) tag, and an IC tag. In particular,an ID chip comprising an antenna and an integrated circuit formed over asemiconductor substrate has been put to practical use now.

DISCLOSURE OF INVENTION

The reliability of an ID chip depends on the reliability of asemiconductor element that is used for an integrated circuit of the IDchip. Increasing the reliability of the semiconductor element allows toease environmental conditions to use the ID chip, thereby expanding therange of application concerning the ID chip. However, it is assumed thatthe semiconductor element is contaminated with alkali metal such as Na,alkali earth metal and moisture, depending on the environment to be usedwith the ID chip. When the alkali metal, the alkali earth metal ormoisture is dispersed in a semiconductor film used in the semiconductorelement, the characteristics of the semiconductor element aredeteriorated, and therefore, the reliability of the ID chip is hardlyimproved.

The ID chip can further be miniaturized as compared with a magneticcard, a bar code and the like, and therefore, the application range ofthe ID chip has been expected to be enlarged. In turn, it is assumedthat the ID chip be attached to a material with flexibility (a flexiblematerial) such as a paper and plastics depending on the intendedpurpose. However, a semiconductor substrate has lower mechanicalstrength than those of the above magnetic card and bar code. When the IDchip is formed over a packing material, a certificate, a bank note, aportfolio and the like, each of which uses a flexible material as itssupport medium, there is a probability that the ID chip is damaged inuse. Therefore, the ID chip has been not feasible.

The mechanical strength of the ID chip can be improved to some extent byreducing the dimension of the ID chip itself. In this case, however, acircuit with the adequate scale is hardly ensured, which results inlimitation in the application of the ID chip. This is not preferable.Meanwhile, when it is emphasized that the enough scale of the circuit isensured, the dimension of the ID chip cannot be reduced randomly so thatthe improvement of the mechanical strength is limited.

In the case of using an ID chip formed using the semiconductorsubstrate, the semiconductor substrate serves as a conductor to blockradio waves. Accordingly, there is a drawback in which signals areeasily attenuated depending on the direction of transmitting the radiowaves.

In view of the above problems in the conventional art, the presentinvention has an object to provide a semiconductor device which iscapable of increasing the reliability of a semiconductor element andimproving the mechanical strength without suppressing the scale of acircuit.

The semiconductor device of the present invention uses a TFT (thin filmtransistor), which is formed using an electrically-isolatedsemiconductor thin film, as its integrated circuit. The integratedcircuit is sandwiched with films formed by laminating plural insulatingfilms (hereinafter referred to as sealing films).

Each sealing film includes plurality insulating films made from aninorganic material (hereinafter, a barrier film) that can prevent thealkali metal such as Na, alkali earth metal, moisture and the like frompenetrating into a semiconductor film included in a semiconductorelement and an insulating film with lower stress than the barrier film(hereinafter, a stress relaxation film). Each sealing film may includeone or plural stress relaxation films, wherein one or plural stressrelaxation films are formed between the barrier films.

As the barrier films which can prevent the alkali metal, alkali earthmetal, moisture and the like from penetrating into the semiconductorfilm, inorganic insulating films typified by silicon nitride, siliconnitride oxide and the like can be used.

The integrated circuit may be formed over a substrate. Or, after formingthe integrated circuit over a substrate, it may be separated from thesubstrate to be attached to a flexible substrate (or, with flexibility),which is separately prepared. The ID chip of the invention can be in theform of an ID chip comprising an antenna along with the integratedcircuit. The integrated circuit is operated by using an alternatingvoltage generated in the antenna. By modulating the alternating voltageapplied to the antenna, the integrated circuit can send a signal to areader/writer. The antenna may be formed along with the integratedcircuit, or may be formed individually such that it is electricallyconnected to the integrated circuit later.

The attachment of the integrated circuit may, for example, be carriedout according to various kinds of methods as follows. A metal oxide filmis formed between a high heat resistant substrate and an integratedcircuit, and the metal oxide film is weakened to separate the integratedcircuit from the substrate so that the integrated circuit is attached toan abject. Or, a separation layer is provided between a high heatresistant substrate and an integrated circuit, the separation film isremoved by irradiation of laser beam or by etching to separate theintegrated circuit from the substrate so that the integrated circuit isattached to an object. Or, a high heat resistant substrate over which anintegrated circuit is formed is mechanically removed or is removed byetching using a solution or a gas to separate the integrated circuitfrom the substrate, thereby attaching the integrated circuit to anobject.

Also, by attaching integrated circuits, which are formed separately, toone another, the integrated circuits may be laminated such that thescale of the circuits or the memory capacity is increased. Since therespective integrated circuits are dramatically thin in thickness ascompared with an ID chip manufactured using a semiconductor substrate,the mechanical strength of an ID chip can be maintained to some extenteven when the plural integrated circuits are stacked together. Thestacked integrated circuits can be connected to one another by using aknown connection method such as flip chip technology, a TAB (tapeautomated bonding) technology and a wire bonding technology.

The use of the barrier films can prevent the alkali metal, alkali earthmetal, moisture and the like from dispersing in the semiconductor film,thereby improving the reliability of the semiconductor element. Theinorganic insulating films used for the barrier films have relativelylarge stress, and hence, there is a possibility that the use of theinorganic insulating films adversely affects the characteristics of thesemiconductor element, e.g., the mobility is varied. According to theinvention, however, since the sealing films including a stressrelaxation film that is formed between the barrier films are employed,the stress of the barrier films is alleviated, thereby preventing thecharacteristics of the semiconductor element from being adverselyaffected.

To inhibit ingress of the alkali metal, alkali earth metal, moisture andthe like into the semiconductor film, plural barrier films are providedin the invention rather than simply increasing the thickness of abarrier film. Therefore, the stress per a sheet of the barrier films canbe suppressed, which prevents the respective barrier films from crackingalong with the ingress of the alkali metal, alkali earth metal, moistureand the like into the semiconductor film.

In the case of using a flexible substrate such as a plastic substrateand a paper as a substrate to be formed with an ID chip, it is assumedthat the substrate becomes stressed. According to the invention,however, since the plural barrier films are provided, the stress per asheet of the barrier films is suppressed. In addition, the stress can bealleviated to some extent by the stress relaxation film. Consequently,it is possible to prevent the adverse effects on the semiconductorelement due to the stress or the ingress of the alkali metal, alkaliearth metal, moisture and the like into the semiconductor film.

Generally, the flexible substrate such as the plastic substrate and thepaper tends to be permeated with moisture easily as compared with aglass substrate, a semiconductor substrate and the like. Since thebather films are used in the present invention, ingress of moisture intothe semiconductor film can be prevented even in the case of using theforegoing flexible substrate.

The flexible substrate such as the plastic substrate and the paper isgenerally inferior in the heat resistance property as compared with theglass substrate, the semiconductor substrate and the like. According tothe invention, since a film deposition temperature is set to be low inconsideration of the heat resistance property of the flexible substrate,the quality of a barrier film may be deteriorated. However, the pluralbarrier films are laminated according to the invention, therebypreventing the alkali metal, alkali earth metal and moisture frompenetrating into the semiconductor film.

The ID chip of the invention is formed with an integrated circuit thatis formed by using an electrically-isolated TFT so that a flexiblesubstrate can be employed. In this case, high mechanical strength can beobtained without increasing the dimension of the ID chip as much as anID chip using a semiconductor substrate. Accordingly, the mechanicalstrength of the ID chip can be improved, thereby enlarging theapplication range of the ID chip without suppressing the scale of thecircuit.

Furthermore, the ID chip according to the invention comprises advantagesas follows. Since the integrated circuit is formed using theelectrically-isolated TFT in the ID chip of the invention, a parasiticdiode is hardly formed between the integrated circuit and the substrate,unlike a transistor formed over a semiconductor substrate. Therefore, alarge amount of current does not flow through a drain region due to apotential of an alternating-current signal that is applied to a sourceor a drain region, which hardly causes the deterioration or failure. Ascompared with an ID chip using a semiconductor substrate, radio wavesare hardly blocked in the ID chip of the invention so that a signal canbe prevented from being attenuated due to blocking of the radio waves.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1A is an external view and FIGS. 1B and 1C are cross sectionalviews of an ID chip according to the present invention;

FIGS. 2A to 2D are cross sectional views showing a method ofmanufacturing an ID chip according to the invention;

FIGS. 3A to 3C are cross sectional views showing a method ofmanufacturing an ID chip according to the invention;

FIGS. 4A and 4B are cross sectional views showing a method ofmanufacturing an ID chip according to the invention;

FIGS. 5A to 5C are cross sectional views showing a method ofmanufacturing an ID chip according to the invention;

FIGS. 6A and 6B are cross sectional views of ID chips according to theinvention;

FIGS. 7A to 7D are diagrams showing a method of manufacturing aplurality of ID chips of the invention by using a large size substrate;

FIG. 8 is an external view of an ID chip that becomes stressed;

FIG. 9 is a block diagram showing one mode of an ID chip with afunctional structure according to the invention;

FIGS. 10A and 10C are top views and FIGS. 10B and 10D are crosssectional views showing the shape of grooves, which are formed forseparating a plurality of integrated circuits formed over a substrate;

FIGS. 11A to 11C are diagrams showing examples of application for an IDchip according to the invention;

FIGS. 12A and 12B are diagrams showing examples of application for an IDchip according to the invention;

FIGS. 13A to 13D are cross sectional views showing structures of a TFTthat is used in an ID chip according to the invention;

FIG. 14 is a cross sectional view of an ID chip according to theinvention; and

FIG. 15 is a cross sectional view of an ID chip according to theinvention.

BEST MODE FOR CARRYING OUT THE INVENTION

The embodiment mode according to the present invention will hereinafterbe described with reference to the accompanying drawings. The presentinvention can be carried out in many different modes, and it is easilyunderstood by those who skilled in the art that embodiments and detailsherein disclosed can be modified in various ways without departing fromthe purpose and the scope of the invention. It should be noted that thedescription of the embodiment modes to be given below should not beinterpreted as being limited to the invention.

A structure of an ID chip according to the invention will be describedwith reference to FIGS. 1A to 1C. FIG. 1A is a perspective view of onemode for the ID chip and FIG. 1B is a cross sectional view taken along aline A-A′ of FIG. 1A, wherein reference numeral 100 indicates anintegrated circuit and reference numeral 101 indicates an antenna. Theantenna 101 is electrically connected to the integrated circuit 100.Reference numeral 102 denotes a substrate and reference numeral 103denotes a cover member. The integrated circuit 100 is sandwiched betweenthe substrate 102 and the cover member 103.

A state in which the antenna 101 along with the integrated circuit 100are sandwiched between the substrate 102 and the cover member 103 isshown in FIG. 1A. The present invention is not particularity limited tothe structure. For instance, the antenna 101 may be formed on anotherface of the cover member 103 that is opposite side of the face incontact with the substrate 102 and an opening may be formed in the covermember 103 such that the integrated circuit 100 and the antenna 101 areelectrically connected to each other through the opening.

An enlarged view of a cross section for the ID chip, which correspondsto a portion surrounded by a dashed line 104 in FIG. 1B, is shown inFIG. 1C. A TFT 105 coincides with one of semiconductor elements that areused in the integrated circuit 100. Although FIG. 1C shows the TFT asone of the semiconductor elements used in the integrated circuit 100,the present invention is not limited to the structure. Various kinds ofcircuit elements can be used as the semiconductor elements for theintegrated circuit. In addition to the TFT, for example, a memoryelement, a diode, a photoelectric conversion element, a resistiveelement, a coil, a capacitor element, an inductor and the like cantypically be employed.

The TFT 105 is sandwiched between sealing films 106 and 107. Concretely,the sealing film 106 is provided between the substrate 102 and the TFT105, while the sealing film 107 is provided between the cover member 103and the TFT 105. The sealing film 106 includes a barrier film 106 a, astress relaxation film 106 b and a barrier film 106 c, which aresequentially laminated on the substrate 102. The sealing film 107includes a barrier film 107 a, a stress relaxation film 107 b and abarrier film 107 c, which are sequentially laminated over the TFT 105.

FIG. 1C shows an example in which the sealing films 106 and 107 comprisethe stress relaxation films 106 b and 107 b, respectively, however, thepresent invention is not limited to the configuration. When each sealingfilm includes three or more barrier films, plural stress relaxationfilms may be provided between the barrier films.

The barrier films 106 a, 106 c, 107 a and 107 c are made from pluralinorganic insulating films so as to prevent alkali metal such as Na,alkali earth metal, moisture and the like from penetrating into asemiconductor film used in the semiconductor element. For example,silicon nitride, silicon nitride oxide, aluminum oxide, aluminumnitride, aluminum nitride oxide, aluminum silicon nitride oxide and thelike can be employed as the barrier films 106 a, 106 c, 107 a and 107 c.

The stress relaxation films 106 b and 107 b can be made from insulatingfilms with lower stress as compared with the barrier films 106 a, 106 c,107 a and 107 c. For instance, polyimide, acrylic, polyamide, polyimideamide, benzocyclobutene, epoxy resin and the like can be used as thestress relaxation films 106 b and 107 b.

Although the example in which the mechanical strength of the ID chip isimproved by using the cover member 103 is shown in FIGS. 1A to 1C, theID chip of the invention does not necessarily use the cover member 103.For example, the mechanical strength of the ID chip according to theinvention can be improved by coating the surface of the sealing film 107with a resin etc.

The integrated circuit 100 may be formed on the substrate 102 directlyif the substrate 102 has a heat resistance property, which can withstandheat treatment in the step of manufacturing the integrated circuit 100.When using a substrate, which is inferior in the heat resistance, like aplastic substrate, after forming the integrated circuit over a heatresistant substrate, the integrated circuit may be separated from theheat resistant substrate and then attached to a flexible substrate likeplastics, which is separately prepared. In this case, the integratedcircuit along with the sealing films may be formed over the heatresistant substrate previously so that both the integrated circuit andthe sealing films may be attached to the flexible substrate after theyare separated from the heat resistant substrate. Or, a sealing film maybe formed over the flexible substrate in advance so that the integratedcircuit is attached to the sealing film.

When attaching the integrated circuit along with the sealing films tothe flexible substrate, the alkali metal, alkali earth metal, moistureand the like can be prevented from intruding into the semiconductor filmincluded in the semiconductor element in a series of steps fromseparating to attaching due to the sealing films. In the series ofsteps, even when some of the plural barrier films that are included inthe sealing films are cracked by applying stress to the sealing films orthe integrated circuit in some sort of trigger, the other barrier filmscan prevent the ingress of the alkali metal, alkali earth metal,moisture and the like. Also, in the series of the steps, when thesealing films or the integrated circuit become stressed, deteriorationin the characteristics of the semiconductor elements can be prevented byalleviating the stress.

Next, a method of manufacturing the ID chip according to the inventionwill be described in more detail below. Note that although theembodiment mode shows the electrically-isolated TFT as one of thesemiconductor elements, the present invention is not limited thereto,and various types of circuit elements can be used as the semiconductorelements that are included in the integrated circuit.

As shown in FIG. 2A, a separation layer 501 is formed over a heatresistant substrate (i.e., a first substrate) 500 by sputtering. As thefirst substrate 500, a substrate that can withstand a processingtemperature in the subsequent manufacturing steps, for example, a glasssubstrate such as a barium borosilicate glass and a alumino borosilicateglass is employed.

As the separation layer 501, a layer containing silicon as its principalconstituent such as amorphous silicon, polycrystalline silicon, singlecrystalline silicon and microcrystalline silicon (includingsemiamorphous silicon) can be employed. The separation layer 501 can beformed by sputtering, plasma CVD and the like. In the embodiment mode,amorphous silicon with a thickness of about 500 nm is formed bysputtering as the separation layer 501. The material for the separationlayer 501 is not particularly limited to silicon, and the separationlayer can be made from a material, which can be removed easily andselectively by etching.

A sealing film 502 is formed over the separation layer 501. The sealingfilm 502 may include at least two or more barrier films and one or morestress relaxation films sandwiched between the barrier films.

In the embodiment mode, for instance, a barrier film 502 a, a stressrelaxation film 502 b and a barrier film 502 c are sequentiallylaminated on the separation layer 501. The bather films 502 a and 502 care, for example, formed of silicon nitride by sputtering. The stressrelaxation film 502 b is, for example, formed of polyimide.

Silicon nitride used for forming the barrier films 502 a and 502 c areformed by introducing argon while maintaining a substrate temperature of150° C. at sputtering pressure of about 0.4 Pa. Then, the siliconnitride is achieved by using silicon as a target and introducingnitrogen and hydrogen in addition to the argon. In the case of usingsilicon nitride oxide as the barrier films 502 a and 502 c, siliconnitride oxide is formed by introducing argon while maintaining asubstrate temperature of 150° C. at sputtering pressure of about 0.4 Pa.Then, the silicon nitride oxide is completed by using silicon as atarget and introducing nitrogen, nitrogen dioxide and hydrogen inaddition to the argon. Note that silicon oxide may be used as the targetin place of silicon.

The thicknesses of the barrier films 502 a and 502 c are desirably inthe range of 50 nm to 3 μm. Silicon nitride films are, herein, formedwith a thickness of 1 μm. The method for forming the barrier films isnot limited to the sputtering, and an operator can select the methodarbitrarily. For example, LPCVD, plasma CVD and the like can beemployed.

The barrier films 502 a and 502 c can be made from silicon nitrideoxide, aluminum oxide, aluminum nitride, aluminum nitride oxide oraluminum silicon nitride oxide (AlSiON), as substitute for siliconnitride. Since aluminum silicon nitride oxide has a relatively highthermal conductivity, when the barrier films are made from aluminumsilicon nitride oxide, heat generated in the semiconductor elements canbe released efficiently.

The stress relaxation film 502 b is made from a transparent resin.Typically, polyimide, acrylic, polyamide, polyimide amide,benzocyclobutene, epoxy resin and the like can be employed. Resinsexcept of the foregoing resin can be used. Here, heat-polymerizingpolyimide is applied and baked to form the stress relaxation film 502 b.

The thickness of the stress relaxation film 502 b is preferably in therange of 200 nm to 2 μm. In the embodiment mode, polyimide with athickness of 1 μm is farmed.

The barrier films 502 a, 502 c and the stress relaxation film 502 b arenecessary to be made from materials capable of achieving selectivityupon removing the separation layer 501 later.

The sealing film 502 is formed to prevent alkali metal such as Na,alkali earth metal and moisture, which are contained in a secondsubstrate and an adhesive agent, from penetrating into the semiconductorelements upon attaching the semiconductor elements to the secondsubstrate with the adhesive agent so as not to adversely affect thecharacteristics of the semiconductor elements. Further, the sealing film502 serves to protect the semiconductor elements from etchant uponetching the separation layer 501.

A semiconductor film is next formed on the sealing film 502. Preferably,the semiconductor film is formed without being exposed to atmosphericair after forming the sealing film 502. The thickness of thesemiconductor film is set to be 20 to 200 nm (desirably, 40 to 170 nm,more preferably, 50 to 150 nm). The semiconductor film may be anamorphous semiconductor, a semiamorphous semiconductor or apolycrystalline semiconductor. The semiconductor film may contain eithersilicon or silicon germanium. When using silicon germanium, theconcentration of germanium is preferably set to be about 0.01 to 4.5atomic %.

The semiconductor film may be crystallized by a known method. As theknown crystallization method, there are laser crystallization usinglaser beam, crystallization using a catalytic element and the like. Or,a method in combination of the crystallization using a catalytic elementand the laser crystallization can be used. When an excellent heatresistant substrate like quartz is used as the substrate 500, thermalcrystallization using an electrically-heated furnace, lamp annealingcrystallization using infrared light, crystallization using a catalyticelement, crystallization in combination with high temperature annealingof about 950° C. or the like can be used.

In the case of laser crystallization, for example, the semiconductorfilm is subjected to thermal annealing at a temperature of 500° C. forone hour to enhance a resistance property with respect to laser beamprior to performing laser crystallization. A continuous wave solid-statelaser is used and laser beam with second to fourth harmonics isirradiated to the semiconductor film to obtain a crystal with a largegrain size. Typically, for instance, the second harmonic (532 nm) or thethird harmonic (355 nm) of Nd:YVO₄ laser (fundamental wave with 1064 nm)is preferably used. Concretely, laser beam emitted from the continuouswave YVO₄ laser is converted into a harmonic by a nonlinear opticalelement to obtain laser beam with 10 W output. The laser beam ispreferably formed to have a rectangular shape or an elliptical shape ona surface of the semiconductor film to be irradiated with the laserbeam. In this case, the power density of about 0.01 to 100 MW/cm²(preferably, 0.1 to 10 MW/cm²) is required. The scanning rate isapproximately set to be about 10 to 2,000 cm/sec to irradiate thesemiconductor film.

While the oscillation frequency of pulsed laser beam is set to be 10 MHzor more, laser crystallization may be carried out using an extremelyhigher frequency band than a frequency band of several tens Hz toseveral hundreds Hz, which is generally used. The period formirradiating pulsed laser beam to the semiconductor film to curing thesemiconductor film completely is considered to be several tens nsec toseveral hundreds nsec. By utilizing the above-mentioned frequency band,next pulsed laser beam can be irradiated to the semiconductor film untilthe semiconductor film is melted due to irradiation of laser beam andsolidified. Therefore, a solid-liquid interface can be movedcontinuously on the semiconductor film so that the semiconductor filmhaving crystal grains, which are continuously grown in the scanningdirection, can be formed. Specifically, an aggregate of crystal grainseach of which has a width in a scanning direction of 10 to 30 μm and awidth in a direction perpendicular to the scanning direction of 1 to 5μm can be obtained. By forming the single crystal grains growing towardthe scanning direction, the semiconductor film in which almost nocrystal grain boundary is formed in a channel direction of a TFT can beformed.

With respect to the laser crystallization, continuous wave laser beam ofa fundamental wave may be irradiated in parallel with continuous wavelaser beam of a higher harmonic. Or, continuous wave laser beam of afundamental wave may be irradiated in parallel with pulsed laser beam ofa higher harmonic.

Laser beam may be irradiated under an inert gas atmosphere such as raregas and nitrogen gas. This suppresses the surface roughness of thesemiconductor due to irradiation of laser beam so that variation in thethreshold value caused by fluctuation in the interface state density canfurther be suppressed.

By irradiating laser beam to the semiconductor film above, thesemiconductor film with improved crystallinity can be formed. Note thata polycrystalline semiconductor may previously be formed by sputtering,plasma CVD, thermal CVD or the like.

Although the semiconductor film is crystallized in the embodiment mode,an amorphous semiconductor or a microcrystalline semiconductor may bekept intact and subjected to subsequent processing without beingcrystallized. As compared with the TFT using a polycrystallinesemiconductor, a TFT using the amorphous or microcrystallinesemiconductor requires less number of manufacturing steps, and hence,has an advantage of suppressing cost and improving yield.

The amorphous semiconductor can be obtained by performing glow dischargedecomposition with silicide gas. Typically, SiH₄ and Si₂H₆ are cited asthe silicide gas. These silicide gases can be diluted with hydrogen orhydrogen and helium.

The semiamorphous semiconductor is a film containing a semiconductorwith an intermediate structure between an amorphous semiconductor and acrystalline semiconductor (including a single crystal structure and apolycrystalline structure). The semiamorphous semiconductor has a thirdcondition that is stable in term of free energy, and includes acrystalline region having a short range order along with latticedistortions. A crystal region with a size of 0.5 to 20 nm can bedispersed in the semiamorphous semiconductor. Raman spectrum is shiftedtoward lower wavenumbers than 520 cm⁻¹. The diffraction peaks of (111)and (220), which are believed to be derived from silicon crystallattice, are observed in the semiamorphous semiconductor by X-raydiffraction. The semiamorphous semiconductor contains hydrogen orhalogen of at least 1 atomic % or more as a neutralizing agent fordangling bonds. The semiamorphous having the above mentioned structuresis, herein, referred to as the semiamorphous semiconductor (SAS) for thesake of convenience. The lattice distortions are further extended byadding an rare gas element such as helium, argon, krypton and neon sothat the favorable semiamorphous semiconductor with improved reliabilitycan be obtained.

The SAS is formed by glow discharge decomposition with silicide gas.SiH₄ is a representative silicide gas. In addition to SiH₄, Si₂H₆,SiH₂Cl₂, SiHCl₃, SiCl₄, SiF₄ and the like can be used as the silicidegas. The silicide gas may also be diluted with hydrogen, or a mixture ofhydrogen and one or more of rare gas elements selected from helium,argon, krypton, and neon such that the SAS is easily formed. Thedilution ratio is set to be in the range of 1:2 to 1:1,000. In addition,a carbide gas such as CH₄ and C₂H₆ or germanium gas such as GeH₄ andGeF₄ or F₂ may be mixed in the silicide gas so that the width of theenergy band may be adjusted in the range of 1.5 to 2.4 eV or 0.9 to 1.1eV.

In the case of forming a semiamorphous semiconductor with a gascontaining a mixture of SiH₄ and H₂ or a gas containing a mixture ofSiH₄ and F₂, for example, when a TFT is manufactured using thesemiamorphous semiconductor, the subthreshold coefficient (S value) ofthe TFT can be set to be 0.35 V/sec or less, typically, 0.25 to0.09V/sec, while the mobility thereof can be set to be 10 cm²/Vsec. Whena ring oscillator is formed by using the TFT using the above amorphoussemiconductor, for example, the ring oscillator can be operated at thedrive voltage of about 3 to 5 V and at 10 MHz or more. The frequencycharacteristics for each stage can be set to be 100 kHz or more,preferably, 1 MHz or more, at the drive voltage of about 3 to 5 V.

As shown in FIG. 2A, the semiconductor film is patterned to form anisland-like semiconductor film 503. As shown in FIG. 2B, various kindsof semiconductor elements typified by a TFT is formed utilizing theisland-like semiconductor film 503. Although the sealing film 502 andthe island-like semiconductor film 503 are in contact with each otherin. FIG. 2B, an electrode, an insulating film and the like may be formedbetween the sealing film 502 and the island-like semiconductor film 503depending on the kinds of the semiconductor elements to be formed. Whenforming a bottom-gate TFT that is a kind of the semiconductor element,for example, a gate electrode and a gate insulating film are formedbetween the sealing film 502 and the island-like semiconductor film 503.

In FIG. 2B, a top-gate TFT 504 is formed using the island-likesemiconductor film 503. Concretely, a gate insulating film 507 is formedso as to cover the island-like semiconductor film 503, and a conductivefilm is formed on the gate insulating film 507 and patterned to form agate electrode 508. While utilizing the gate electrode 508 or a patternformed of a resist as a mask, an impurity imparting an n-typeconductivity is doped into the island-like semiconductor film 503 so asto form a source region, a drain region, an LDD region and the like. TheTFT 504 is, herein, formed to be of an n-type conductivity.Alternatively, when forming a p-type TFT, an impurity imparting a p-typeconductivity is doped into the island-like semiconductor film. Accordingto the above steps, the TFT 504 can be obtained.

After forming the gate insulating film 507, heat treatment may becarried out at 300 to 450° C. for 1 to 12 hours under an atmospherecontaining 3 to 100% hydrogen so as to hydrogenate the island-likesemiconductor film 503. As other hydrogenation method, plasmahydrogenation (using hydrogen excited by plasma) can be performed.Through the hydrogenation step, dangling bonds can be terminated by thethermally excited hydrogen. If defects are caused in the semiconductorfilm by bending a second flexible substrate after attaching thesemiconductor elements to the second flexible substrate in thesubsequent step, the concentration of hydrogen contained in thesemiconductor film is set to be 1×10¹⁹ to 1×10²² atoms/cm³, preferably,1×10¹⁹ to 5×10²⁰ atoms/cm³ by hydrogenation such that the defects can beterminated by the hydrogen contained in the semiconductor film. Or,halogen may be contained in the semiconductor film to terminate thedefects.

Note that the method for manufacturing the is not limited to the aboveconfiguration.

A passivation film 505 is next formed to cover the TFT 504. Desirably,the passivation film 505 is made from a silicon nitride film or asilicon nitride oxide film so as to prevent the alkali metal or alkaliearth metal from penetrating into the TFT 504. Since the TFT 504 iscovered with the sealing film 502 and the passivation film 505, thealkali metal such as Na and alkali earth metal, which adversely affectthe characteristics of the semiconductor elements, can be prevented fromintruding into the semiconductor film that is used in the semiconductorelement.

A first interlayer insulating film 510 is formed to cover thepassivation film 505. A contact hole is formed in the gate insulatingfilm 507, the passivation film 505 and the first interlayer insulatingfilm 510, and wirings 513 and 514 are formed on the first interlayerinsulating film 510 such that they are connected to the TFT 504 via thecontact hole.

As shown in FIG. 2C, a second interlayer insulating film 515 is nextformed on the first interlayer insulating film 510. The secondinterlayer insulating film 515 is formed to have an opening such thatthe wiring 514 is partly exposed. As the first and second interlayerinsulating films 510 and 515, an organic insulating film, an inorganicinsulating film, an insulating film containing a Si—O—Si bond that isformed using siloxane material as a start material (hereinafter,referred to as a siloxane insulating film) and the like can be employed.The siloxane insulating film includes at least one kind of fluorine,alkyl group and aromatic hydrocarbon as its substituent, in addition tohydrogen.

As shown in FIG. 2D, an antenna 519 is formed on the second interlayerinsulating film 515. The antenna 519 can be formed of a conductivematerial containing one or more of metals such as Ag, Au, Cu, Pd, Cr,Mo, Ti, Ta, W and Al or metal compounds. The antenna 519 is connected tothe wiring 514. Although the antenna 519 is directly connected to thewiring 514 in FIG. 2D, the ID chip of the present invention is notlimited to the structure. For example, the antenna 519 and the wiring514 may be electrically connected to each other by using a wiring thatis separately formed.

The antenna 519 is formed by the printing method, the photolithography,the vapor deposition, the droplet discharging method, and the like.Although the antenna 519 is formed using a single-layer conductive filmin the embodiment mode, it may be formed by laminating plural conductivefilms.

The droplet discharging method indicates a method for forming apredetermined pattern by discharging a droplet containing a prescribedcomposition through a fine hole, and includes the ink jet method and thelike in the category. The printing method includes the screen printingmethod, the offset printing method and the like. By using the printingmethod or the droplet discharging method, the antenna 519 can be formedwithout using a mask for exposure. Differing from the photolithographyin which loss of materials is caused by etching, the droplet dischargingmethod and the printing method can utilize materials efficiently. Inaddition, cost that goes into the making of the ID chip can besuppressed since an expensive mask for exposure is not required.

When using the droplet discharging method or the various kinds ofprinting methods, for example, a conductive particle in which Cu iscoated with Ag can also be used. In the case where the antenna 519 isformed by the droplet discharging method, the surface of the secondinterlayer insulating film 515 is desirably treated to increase theadhesion of the surface with respect to the antenna 519, in advance.

In order to increase the adhesion of the surface of the secondinterlayer insulating film, for example, the following three methods anbe mentioned. A metal or a metal compound that can improve the adhesionof a conductive film or an insulating film due to catalytic action isattached to the surface of the second interlayer insulating film 515. Anorganic insulating film, a metal, and a metal compound each of which iswell-adhered to a conductive film or an insulating film are attached tothe surface of the second interlayer insulating film 515. The surface ofthe second interlayer insulating film 515 is subjected to plasmaprocessing under atmospheric pressure or reduced pressure to change theproperties of the surface thereof. As the metal, which is well-adheredto the conductive film or the insulating film, titanium, titanium oxide,3d transition elements such as Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn andthe like can be cited. As the metal compound, oxide, nitride, andoxynitride of the above-mentioned metals can be cited.

When the metal or the metal compound to be attached to the secondinterlayer insulating film 515 has conductivity, the sheet resistance iscontrolled so as not to hinder the normal operation of the antenna.Concretely, the average thickness of the metal or the metal compoundwith the conductivity may be controlled to be, for example, 1 to 10 nm.Or, the metal or the metal compound may be partly or entirely oxidizedto be insulated. Or, in a region other than a region in which theadhesion is intended to be improved, the metal or the metal compound maybe selectively removed by etching. Or, the metal or the metal compoundmay be selectively attached to a certain region of the second interlayerinsulating film by the droplet discharging method, the printing method,the sol-gel method, etc. rather than attaching it on the entire surfaceof the second interlayer insulating film. The metal or the metalcompound is not necessary to have a completely continuous shape like afilm on the surface of the second interlayer insulating film 515.Alternatively, a plurality of disconnected patterns of the metal ormetal compound may be formed. As the organic insulating film, forexample, polyimide, siloxane insulating film can be cited.

After forming the antenna 519, a protective layer 521 is formed over thesecond interlayer insulating film 515 so as to cover the antenna 519.The protective layer 521 is made from a material that can protect theantenna 519 upon removing the separation layer 501 by etching in thesubsequent step. For example, a water or alcohol-soluble epoxy resin,acrylate resin or silicon resin is applied to the entire surface of thesecond interlayer insulating film to form the protective layer 521.

For forming the protective layer 521 in the embodiment mode, awater-soluble resin (#VL-WSHL10 manufactured by Toagosei Co., Ltd.) isapplied over the second interlayer insulating film by spin coating tohave a thickness of 30 μm and exposed for 2 minutes so as to be curedtemporarily. The water-soluble resin is further exposed to UV light froma rear face of the substrate for 2.5 minutes and from a top face thereoffor 10 minutes, i.e., for 12.5 minutes in total to be cured completely,thereby obtaining the protective layer 521. When plural kinds of organicresins are laminated to one another, they might be partly dissolved inapplication or baking or adhesion thereof might be excessively increaseddepending on the sorts of solvents contained in the organic resins.Therefore, when the second interlayer insulating film 515 and theprotective layer 521 are both made from organic resins that are solublein a same solvent, an inorganic insulating film (e.g., an SiN_(X) film,an SiN_(X)O_(Y) film, an AlN_(X) film or AlN_(X)O_(Y) film) ispreferably formed to cover the second interlayer insulating film 515such that the protective layer 521 is smoothly removed in the subsequentstep.

As shown in FIG. 3A, a groove 522 is formed to separate the ID chipsfrom one another. The groove 522 may be provided to expose theunderlying separation layer 501. The groove 522 can be formed by dicing,scribing, or the like. When the ID chips formed over the first substrate500 is not necessarily to be divided, the groove 522 may not necessarilybe formed.

As shown in FIG. 3B, the separation layer 501 is removed by etching. Inthe embodiment mode, halide is used as an etching gas and it isintroduced through the groove 522. For example, ClF₃ (chlorinetrifluoride) is employed, and etching is carried out under theconditions as follows: a temperature is set to be 350° C.; a flow rate,300 sccm; a pressure, 6 Torr; and time, 3 hours. Or, ClF₃ gas mixed withnitrogen may be used. By using the halide such as ClF₃, NF₃ (nitrogentrifluoride), BrF₃ (bromine trifluoride) and HF (hydrogen fluoride), theseparation layer 501 is selectively etched so that the first substrate500 can be separated from the TFT 504. In case of using HF, a siliconoxide film is employed as the separation layer. Note that the halide maybe either a gas state or a solid state.

As shown in FIG. 3C, the separated TFT 504 and the antenna 519 areattached to a second substrate 531 with an adhesive agent 530. Amaterial that can attach the second substrate 531 and the sealing film502 to each other is employed for the adhesive agent 530. As theadhesive agent 530, for example, various types of curing adhesive agentsincluding a reactive curing adhesive agent, a thermal curing adhesiveagent, a light curing adhesive agent such as an ultraviolet curingadhesive agent, an anaerobic curing adhesive agent and the like can beused.

With respect to the second substrate 531, a flexible organic materialsuch as a paper and plastics can be used. In addition, a flexibleinorganic material can be employed. As a plastic substrate, ARTON madefrom polynorbornene with a polar radical (which is manufactured by JSRCorporation) can be used. Also, the following materials can be cited asthe plastic substrate: polyester typified by polyethylene terephthalate(PET), polyether sulfone (PES), polyethylene naphthalate (PEN),polycarbonate (PC), nylon, polyether ether ketone (PEEK), polysulfone(PSF), polyetherimide (PEI), polyarylate (PAR), polybutyleneterephthalate (PBT), polyimide, acrylonitrile butadiene styrene resin,polyvinyl chloride, polypropylene, polyvinyl acetate, acrylic resin andthe like. The second substrate 531 desirably has good thermalconductivity of about 2 to 30 W/mK in order to diffuse the heatgenerated from the integrated circuit.

As shown in FIG. 4A, after removing the protective layer 521, anadhesive agent 532 is applied over the second interlayer insulating film515 so as to cover the antenna 519, and then a cover member 533 isattached to the second substrate 531. As well as the second substrate531, a flexible organic material such as a paper and plastics can beused as the cover member 533. The thickness of the adhesive agent 532may be, for example, set to be 10 to 200 μm.

A sealing film 540 is formed over the surface of the cover member 533 inadvance. In the embodiment mode, the sealing film 540 is formed bysequentially laminating a barrier film 540 a, a stress relaxation film540 b and a barrier film 540 c over the cover member 533. The structureand the method of manufacturing the barrier film 540 a, the stressrelaxation film 5406 and the barrier film 540 c can refer thedescription about the sealing film 502, and will not be furtherexplained. The cover member 533 is attached to the second interlayerinsulating film 515 such that the sealing film 540 is sandwiched betweenthe cover member 533 and the TFT 504.

As for the adhesive agent 532, a material capable of attaching the covermember 533 to the second interlayer insulating film 515 and the antenna519 is employed. For example, various kinds of curing adhesive agentsincluding a reactive curing adhesive agent, a thermal curing adhesiveagent, a light curing adhesive agent such as an ultraviolet curingadhesive agent, an anaerobic curing adhesive agent and the like can beused.

According to the foregoing respective steps, the ID chip is completed.In accordance with the above manufacturing method, the drastically thinintegrated circuit with a thickness in a range of 0.3 μm to 3 μm intotal, typically, about 2 μm can be formed between the second substrate531 and the cover member 533. Note that the thickness of the integratedcircuit includes not only the thickness of the semiconductor elementitself but also the thicknesses of the various types of an insulatingfilm and an interlayer insulating film that are formed between theadhesive agent 530 and the adhesive agent 532. The dimension of theintegrated circuit for the ID chip can be set to be 5 mm square (25 mm²)or less, more desirably, in a range of about 0.3 mm square (0.09 mm²) to4 mm square (16 mm²).

When the integrated circuit is centrally-placed between the secondsubstrate 531 and the cover member 533, the mechanical strength of theID chip can be enhanced. Concretely, when a distance between the secondsubstrate 531 and the cover member 533 is set to be “d”, the thicknessesof the adhesive agent 530 and the adhesive agent 532 are preferablycontrolled such that a distance between the second substrate 531 and thecenter of the integrated circuit in the thickness direction satisfiesthe expression 1 as follows:

d/2−30 μm<x<d/2+30 μm  [Expression 1]

Or, the thicknesses of the adhesive agent 530 and the adhesive agent 532are controlled so as to satisfy the following expression 2:

d/2−10 μm<x<d/2+10 μm  [Expression 2]

In the case where a serial number is stamped into a semiconductor film,an insulating film and the like that are included in an ID chip, whenthe ID chip is illegally flowed into the hands of a third party by theftetc. before data in the ID chip is stored in a ROM, the distributionroute thereof can trace to some extent by the serial number. In thiscase, it is more effective that the serial number be stamped on a partsuch that the serial number is hardly deleted only when a semiconductordevice is disassembled irreparably and unable to be restored.

Although FIG. 4A shows an example using the cover member 533, thepresent invention is not limited to the configuration. For instance,after completion up to the step as shown in FIG. 3C, the sealing film541 may be formed so as to cover the protective layer 521 withoutremoving the protective layer 521, as shown in FIG. 4B. The sealing film541 is formed by sequentially laminating a barrier film 541 a, a stressrelaxation film 541 b and a barrier film 541 c over the protective layer521. The structure and manufacturing method of the barrier film 541 a,the stress relaxation film 541 b and the barrier film 541 c can referthe description about the sealing film 502, and will not be furtherexplained.

The method for separating the integrated circuit from the firstsubstrate 500 is not particularly limited to the etching with use of asilicon film, and other various kinds of methods can be employed. Forexample, a metal oxide film may be formed between the high heatresistant substrate and the integrated circuit and the metal oxide filmis crystallized to be weakened so as to separate the integrated circuitfrom the substrate. Or, for example, the separation layer may bedestroyed by being irradiated with laser beam so that the integratedcircuit is separated from the substrate. Or, for instance, the substrateover which the integrated circuit is formed may be mechanically removedor eliminated by etching using a solution or a gas so as to separate theintegrated circuit from the substrate.

When an organic resin is used as the adhesive agent 530 that is incontact with the sealing film 502 to secure the flexibility of the IDchip, the barrier films 502 a and 502 c included in the sealing film 502are made from silicon nitride films or silicon nitride oxide films,thereby preventing dispersion of the alkali metal such as Na and alkaliearth metal from the organic resin into the semiconductor film.

When an object has a curved surface and the ID chip that is attached tothe object, the second substrate of the ID chip is also curved so as tohave a curved surface drawn by shifting a generating line such as aconical surface and a cylindrical surface. In this case, the directionof the generating line and the direction of moving carriers aredesirably uniformed. This structure can prevent the characteristics ofthe TFT from being adversely affected by curving the second substrate.When the rate of the area for the island-like semiconductor film withinthe integrated circuit is set to be 1 to 30%, it is possible to suppressthe adverse affect of the characteristics for the TFT, even if thesecond substrate is curved.

Although the example in which the antenna and the integrated circuit areformed over the same substrate is shown in the embodiment mode, thepresent invention is not limited to the configuration. Alternatively, anantenna and an integrated circuit that are formed over differentsubstrates may be attached to each other such that the antenna and theintegrated circuit are electrically connected to each other.

Also, the example in which the sealing film 502 and the integratedcircuit are both separated and attached to the substrate is shown in theembodiment mode, however, the present invention is not limited to theconfiguration. A sealing film may be formed over the subject substratein advance to be attached with the integrated circuit. In this case, aninsulating film (a base film) is formed between the separation layer andthe semiconductor element so as to prevent the alkali metal or alkaliearth metal from intruding into the semiconductor film included in thesemiconductor element and protect the semiconductor element in theseparating step.

FIG. 14 is a cross sectional view showing one mode of an ID chip in thecase where a sealing film is formed in advance over the subjectsubstrate to be attached with the integrated circuit. When a sealingfilm 561 is previously formed over the substrate 560 as shown in FIG.14, an adhesive agent 563 is provided between a TFT 562 of theintegrated circuit and the sealing film 561 to attach the TFT 562 andthe sealing film 561 to each other. A base film 564 is next formedbetween the TFT 562 and the adhesive agent 563 to prevent dispersion ofthe alkali metal or alkali earth metal that are contained in theadhesive agent 563 into the semiconductor film used in the semiconductorelement and protect the TFT 562 in the separating step. The base film564 is formed of an inorganic film that can prevent the alkali metalsuch as Na, alkali earth metal, moisture and the like from dispersinginto the semiconductor film included in the semiconductor element. Forinstance, silicon nitride, silicon nitride oxide, aluminum oxide,aluminum nitride, aluminum nitride oxide, aluminum silicon nitride oxideand the like can be used as the base film 564. Note that the base film564 may be formed using a single insulating film or plural insulatingfilms. When the base film 564 is formed using plural insulating films,one of the plural insulating films may be the above-mentioned inorganicinsulating film.

In addition, another sealing film may be formed between the separationlayer and the semiconductor element in addition to the base film formedover the subject substrate to be attached with the integrated circuit.

The method for separating the integrated circuit from the high heatresistant substrate by providing the separation layer between the highheat resistant substrate and the integrated circuit and removing theseparation layer by etching is shown in the embodiment mode, however,the method for manufacturing the ID chip according to the invention isnot limited thereto. For example, a metal oxide film may be providedbetween the high heat resistant substrate and the integrated circuit andthe metal oxide film may be crystallized to be weakened so that theintegrated circuit is separated from the substrate. Or, a separationlayer made from an amorphous semiconductor film containing hydrogen isprovided between the high heat resistant substrate and the integratedcircuit and the separation layer is removed by irradiation with laserbeam so that the integrated circuit may be separated from the substrate.Or, the high heat resistant substrate over which the integrated circuitis formed may be mechanically removed or eliminated by etching using asolution or a gas so that the integrated circuit may be separated fromthe substrate.

Electric waves with the frequency of 13.56 MHz or 2.45 GHz are generallyused for the ID chip. It is very important that the ID chip be formed todetect the radio waves with the foregoing frequency from the viewpointof enhancing the versatility.

As compared with an ID chip formed using a semiconductor substrate, theradio waves are hardly blocked in the ID chip of the embodiment mode sothat the ID chip of the embodiment mode has an advantage of preventingattenuation of signals due to block of the radio waves. Since thesemiconductor substrate is not used, manufacturing cost of the ID chipcan be drastically reduced. For instance, the case of using a siliconsubstrate with 12 inches and the case of using a glass substrate with adimension of 730×920 mm² will be compared as follows. The dimension ofthe silicon substrate is about 73,000 mm² while the dimension of theglass substrate is about 672,000 mm², and therefore, the dimension ofthe glass substrate is about 9.2 times as large as that of the siliconsubstrate. In the glass substrate with the dimension of about 672,000mm², approximately 672,000 of ID chips with 1 mm square are producedregardless of the areas where are consumed by dividing the substrate.The production number is about 9.2 times as large as that of the siliconsubstrate. Since the case of using the glass substrate with 730×920 mm²requires less number of steps as compared with the case of using thesilicon substrate with 12 inches, investment cost in facilities can bereduced about three times. According to the invention, the glasssubstrate can be reused after separating the integrated circuittherefrom. The cost can be reduced significantly as compared with thecase of using the silicon substrate that cannot be reused even if costfor repairing a cracked glass substrate or cleaning the surface of aglass substrate is taken into consideration. If the glass substrate isnot reused and is discarded, since the price of the glass substrate with730×920 mm² is about half of the price of the silicon substrate with 12inches, the cost of manufacturing ID chips can be drastically reduced.

As a consequence, in the case of using the glass substrate with 730×920mm², it is appreciated that the price of an ID chip can be suppressedthirtieth lower than that of an ID chip formed using the silicon filmwith 12 inches. The use of the ID chip as premises for a disposable onehas been expected, and hence, the ID chip according to the inventionthat can be formed by reducing manufacturing cost drastically is veryuseful for the above purpose.

Embodiment 1

In the embodiment, a method for manufacturing an ID chip in which anantenna and an integrated circuit that are formed over differentsubstrates are electrically connected to each other will be described,differing from FIGS. 2A to 2D, FIGS. 3A to 3C, and FIGS. 4A and 4B.

After forming the second interlayer insulating film 515 with an openingas shown in FIG. 2C, a wiring 550 connected to the wiring 514 is formedso as to be in contact with the second interlayer insulating film 515 asshown in FIG. 5A. A protective layer 551 is formed over the secondinterlayer insulating film 515 so as to cover the wiring 550. Thestructure and the manufacturing method of the protective layer 551 canrefer the descriptions with respect to the protective layer 521 as shownin FIG. 2D.

A groove 552 is next formed to separate the ID chips one another. Asshown in FIG. 5B, the separation layer 501 is removed by etching. Thespecific method for forming the groove 552 and the concrete method foretching the separation layer 501 are already shown referring to FIGS. 3Aand 3B, and will not be further explained.

As shown in FIG. 5C, the separated TFT 504 is attached to a secondsubstrate 554 with an adhesive agent 553. A material capable ofattaching the second substrate 554 to the sealing film 502 is used asthe adhesive agent 553. As for the adhesive agent, various types ofcuring adhesive agents including a reactive curing adhesive agent, athermal curing adhesive agent, a light curing adhesive agent such as anultraviolet curing adhesive agent, an anaerobic curing adhesive agentand the like can be used.

After removing the protective layer 551, an adhesive agent 558 isapplied over the second interlayer insulating film 515 so as to coverthe wiring 550, and a cover member 555 is attached thereto. The covermember 555 may be formed of a flexible organic material such as a paperand plastics as well as the second substrate 554.

A sealing film 556 and an antenna 557 are previously formed over thecover member 555. In the embodiment, the sealing film 556 is formed bysequentially laminating a bather film 556 a, a stress relaxation film556 b and a bather film 556 c over the cover member 555. The structureand the manufacturing method of the barrier film 556 a, the stressrelaxation film 556 b and the bather film 556 c can refer to thedescriptions with respect to the sealing film 502, and will not befurther explained. The cover member 555 is attached to the secondinterlayer insulating film 515 such that the sealing film 556 issandwiched between the cover member 555 and the TFT 504.

The antenna 557 is formed opposite side of the sealing film 556 over thecover member 555. The antenna 557 is partly exposed through the contacthole that is formed in the cover member 555 and the sealing film 556. Ananisotropic conductive resin is used as an adhesive agent 558 to connectthe antenna 557 and the wiring 550 to each other electrically.

The anisotropic conductive resin is a material in which a conductivematerial is dispersed in a resin. As the resin, for example, thefollowings can be used: a thermal curing resin such as an epoxy resin,an urethane resin, and an acrylic resin, a thermoplastic resin such as apolyethylene resin and a polypropylene resin, a siloxane resin and thelike. As the conductive material, for example, a plastic particle suchas polystyrene and epoxy that is coated with Ni, Au or the like; Ni; Au;Ag; a metal particle such as solder; particulate or fibrous carbon;fibrous Ni coated with Au and the like can be used. The size of theconductive material is desirably determined in accordance with the pitchbetween the antenna 557 and the wiring 550.

The antenna 557 and the wiring 550 may be pressed to be attached to eachother by applying ultrasonic waves to the anisotropic conductive resinor pressed to be attached to each other by curing the anisotropicconductive resin due to irradiation of ultraviolet light.

Although the present embodiment shows the example of electricallyconnecting the antenna 557 and the wiring 550 with the adhesive agent558 made from the anisotropic conductive resin, the present invention isnot limited to the configuration. As substitute for the adhesive agent558, an anisotropic conductive film may be used to electrically connectthe antenna 557 to the wiring 550 by pressing the anisotropic conductivefilm.

The example in which the sealing film 502 and the integrated circuit areboth separated and attached to the substrate is shown in the embodiment,however, the invention is not limited to the configuration. The sealingfilm may previously be formed over the subject substrate to be attachedwith the integrated circuit. In this case, an insulating film (a basefilm) is formed between the separation layer and the semiconductorelement so as to prevent ingress of the alkali metal or alkali earthmetal into the semiconductor film included in the semiconductor elementand protect the semiconductor element in the separation step. Or,another sealing film may be formed between the separation layer and thesemiconductor element in addition to the sealing film formed in advanceover the subject substrate to be attached with the integrated circuit.

Further, although the embodiment shows the example in which theseparation layer is provided between the high heat resistant substrateand the integrated circuit so that the integrated circuit is separatedfrom the substrate by removing the separation layer by etching, themanufacturing method of the invention is not limited to theconfiguration. For example, a metal oxide film is formed between thehigh heat resistant substrate and the integrated circuit and the metaloxide film is crystallized to be weakened so as to separate theintegrated circuit from the substrate. Or, a separation layer made froman amorphous semiconductor film containing hydrogen may be providedbetween the high heat resistant substrate and the integrated circuit andthe integrated circuit may be separated from the substrate by removingthe separation layer with irradiation of laser beam. Or, the high heatresistant substrate over which the integrated circuit is formed may bemechanically removed or eliminated by etching using a solution or a gasto separate the integrated circuit therefrom.

Although the embodiment shows the example in which the integratedcircuit is separated from the high heat resistant substrate and attachedto the flexible substrate, the present invention is not limited to theconfiguration. When using a substrate that can withstand heat treatmentin the step of manufacturing the integrated circuit, the integratedcircuit is not necessarily separated. FIG. 15 is a cross sectional viewshowing one mode of the ID chip that is formed by using a glasssubstrate.

With respect to the ID chip shown in FIG. 15, a glass substrate is usedas a substrate 560, and a sealing film 561 is formed between a TFT 562used for an integrated circuit and the substrate 560 without sandwichingan adhesive agent therebetween. In the structure, there is nopossibility that the alkali metal such as Ni, alkali earth metal,moisture and the like penetrate into a semiconductor film included in asemiconductor element.

Embodiment 2

A structure of an ID chip in the case of forming a wiring connected to aTFT and an antenna by patterning one conductive film will be explained.FIG. 6A is a cross sectional view of the ID chip according to thepresent embodiment.

In FIG. 6A, reference numeral 601 denotes a TFT. The TFT 601 includes asemiconductor film 602, a gate insulating film 603 for covering thesemiconductor film 602 and a gate electrode 604 that overlaps with thesemiconductor film 602 while sandwiching the gate insulating film 603therebetween. The TFT 601 is covered with a passivation film 605 and afirst interlayer insulating film 606. A wiring 607 formed on the firstinterlayer insulating film 606 is connected to the semiconductor film602 via the gate insulating film 603, the passivation film 605 and thefirst interlayer insulating film 606.

An antenna 608 is formed on the first interlayer insulating film 606.The wiring 607 and the antenna 608 can be made together by forming aconductive film on the first interlayer insulating film 606 andpatterning the conductive film into the respective patterns. By formingthe antenna 608 along with the wiring 607 using the same conductivefilm, the number of steps for manufacturing the ID chip can be reduced.

Embodiment 3

A structure of an ID chip in the case of forming a gate electrode of aTFT along with an antenna by patterning one conductive film will beexplained in the embodiment. FIG. 6B is a cross sectional view of the IDchip according to the present embodiment.

In FIG. 6B, reference numeral 611 denotes a TFT. The TFT 611 includes asemiconductor film 612, a gate insulating film 613 covering thesemiconductor film 612 and a gate electrode 614 that overlaps with thesemiconductor film 612 while sandwiching the gate insulating film 613therebetween. An antenna 618 is formed on the gate insulating film 613.The gate electrode 614 and the antenna 618 can be made together byforming a conductive film on the gate insulating film 613 and patterningthe conductive film into the respective patterns. By forming the antenna618 and the gate electrode 614 together, the number of steps formanufacturing the ID chip can be reduced.

Embodiment 4

In the present embodiment, a method for manufacturing plural ID chipswith use of a large size substrate will be described.

Integrated circuits 701 and antennas 702 are formed over a heatresistant substrate, respectively. The integrated circuits 701 and theantennas 702 are both separated from the heat resistant substrate andattached to a substrate 703 that is separately prepared with an adhesiveagent 704 as shown in FIG. 7A. Although FIG. 7A shows a state in whichplural pairs of the integrated circuits 701 and the antennas 702 arerespectively attached to the substrate 702, the present invention is notlimited to the configuration. Alternatively, the integrated circuits 701and the antennas 702 each of which is connected to one another may beseparated at once and attached to the substrate 703.

As shown in FIG. 7B, a cover member 705 is attached to the substrate 703such that the integrated circuits 701 and the antennas 702 aresandwiched therebetween. At this moment, an adhesive agent 706 isapplied over the substrate 703 so as to cover the integrated circuits701 and the antennas 702. By attaching the cover member 705 to thesubstrate 703, the state as shown in FIG. 7C is obtained. Note that theintegrated circuits 701 and the antennas 702 are illustrated such thatthey are transparent through the cover member 705 in order to show thepositions of the integrated circuits and the antennas clearly.

As shown in FIG. 7D, the integrated circuits 701 and the antennas 702are isolated to one another by dicing or scribing, thereby achieving IDchips 707.

The present embodiment shows the example of separating the antennas 702along with the integrated circuits 701, however, the embodiment is notlimited to the configuration. The antennas may be formed over thesubstrate 703 in advance and the integrated circuits 701 may be attachedto the substrate such that the integrated circuits and the antennas areelectrically connected to each other. Or, after attaching the integratedcircuits 701 to the substrate 703, the antennas may be attached to thesubstrate such that they are electrically connected to the integratedcircuits. Or, the antennas may be formed over the cover member 705 inadvance and the substrate 703 over which the integrated circuits areformed may be attached to the cover member such that the integratedcircuits and the antennas are electrically connected to each other.

When the substrate 703 and the cover member 705 are flexible, the IDchips 707 can be used while being stressed as shown in FIG. 8. In theinvention, the use of the stress relaxation film can allow pressureapplied to the respective ID chips 707 to alleviate to some extent. Inaddition, by providing plural barrier films, stress for each barrierfilm can be suppressed so that adverse effect to the characteristics ofthe semiconductor element due to dispersion of the alkali metal, thealkali earth metal or moisture into the semiconductor element can beprevented.

Note that the ID chip using a glass substrate can be referred to as anIDG chip (identification glass chip) whereas the ID chip using aflexible substrate can be referred to as an IDF chip (identificationflexible ship).

Embodiment 5

The present embodiment will explain a mode of a functional structurewith respect to the ID chip according to the invention.

In FIG. 9, reference numeral 900 denotes an antenna; and 901, anintegrated circuit. The antenna 900 includes an antenna coil 902 and acapacitor element 903 formed inside the antenna coil 902. The integratedcircuit 901 comprises a demodulation circuit 909, a modulation circuit904, a rectification circuit 905, a microprocessor 906, a memory 907 anda switch 908 for applying load modulation to the antenna 900. Pluralmemories may be employed instead of using one memory 907. SRAMs, flashmemories, ROMs, FRAMs (registered trademark) or the like can be used.

Signals sent from a reader/writer as radio waves are modulated intoalternating-current electric signals in the antenna coil 902 byelectromagnetic induction. The alternating-current electric signals aredemodulated in the demodulation circuit 909 and the demodulated signalsare transmitted to the subsequent stage microprocessor 906. A supplyvoltage is generated in the rectification circuit 905 by utilizing thealternating-current electric signals to supply to the subsequent stagemicroprocessor 906.

In the microprocessor 906, various kinds of arithmetic processings areperformed in accordance with the input signals. The memory 907 is storedwith programs, data and the like that are used in the microprocessor906, and it can also be used as a work area in arithmetic processing.The signals sent to the modulation circuit 904 from the microprocessor906 are modulated into alternating-current electric signals. The switch908 can apply load modulation to the antenna coil 902 according to thealternating-current electric signals from the modulation circuit 904.The reader/writer receives load modulation applied to the antenna coil902 by radio waves so that it can read the signals from themicroprocessor 906.

The ID chip of the invention is not necessary to have the antenna 900.When an ID chip does not have the antenna 900, a connection terminal forelectrically connecting to the antenna 900 is provided to the ID chip.

Note that FIG. 9 only shows one embodiment of the ID chip used as a testobject in an inspection apparatus of the invention, and the presentinvention is not limited to the foregoing configuration. The method fortransmitting signals is not limited to the electromagnetic inductionmethod as shown in FIG. 9, and other transmitting methods such as theelectromagnetic coupling method and microwave method can be used.

This embodiment can be implemented by being freely combined withEmbodiments 1 to 4.

Embodiment 6

The embodiment will explain a shape of grooves formed in separatingplural integrated circuits that are formed over a substrate. FIG. 10Aillustrates a top view showing a substrate 803 over which grooves 801are formed. FIG. 10B is a cross sectional view taken along a line A-A′of FIG. 10A.

Integrated circuits 802 are formed on a separation layer 804 and theseparation layer 804 is formed on the substrate 803. The grooves 801 areformed between the respective integrated circuits 802 and have a certaindegree of the depth to expose the separation layer 804. The pluralintegrated circuits 802 are partly separated from one another by thegrooves 801 rather than separating completely.

An etching gas flows through the grooves 801 as shown in FIGS. 10A and10B to remove the separation layer 804 by etching. The condition afterthe etching is depicted in FIGS. 10C and 10D. FIG. 10C corresponds to atop view of the substrate 803 over which the grooves 801 are formedwhile FIG. 10D corresponds to a cross sectional view taken along a lineA-A′ of FIG. 10C. FIG. 10C shows a state in which the separation layer804 is etched inside of a region surrounded by a dashed line. As shownin FIGS. 10C and 10D, the plural integrated circuits 802 are partlyseparated from one another by the grooves 801 while they are partlyconnected to one another so that the respective integrated circuits canbe prevented from being moved due to lack of support after etching theseparation layer 804.

After completing the condition as shown in FIGS. 10C and 10D, a tapeattached with an adhesive agent, another substrate and the like areseparately provided to separate the plural integrated circuits 802 fromthe substrate 803. The separated plural integrated circuits 802 areattached to a support medium before or after separating to one another.

The embodiment mode shows the example of manufacturing the ID chips, andthe method of manufacturing the ID chips according to the invention isnot limited thereto.

This embodiment can be implemented by being freely combined withEmbodiments 1 to 5.

Embodiment 7

The present embodiment will explain application of ID chips according tothe invention.

When the ID chips of the invention are formed using flexible substrates,they are preferably attached to objects having flexibility or a curvedface. When memories such as ROMs that cannot be rewritten are formedinside of integrated circuits included in the ID chips of the invention,forgery of objects attached with the ID chips can be prevented. Forexample, the application of the ID chips of the invention to foods inwhich their commodity values largely depend on production areas andproducers is advantageous to inhibit mislabeling of the production areasand producers with low cost.

Concretely, the ID chips of the invention can be used while beingattached with tags having information about objects such as luggagetags, price tags and name tags. Also, the ID chips themselves of theinvention can be utilized as such tags. For example, the ID chips may beattached to certificates corresponding to documents that prove factssuch as family registers, certificates of residence, passports,licenses, identification cards, member's cards, surveyor's certificates,credit cards, cash cards, prepaid cards, consultation cards and commuterpasses. In addition, for instance, the ED chips may be attached toportfolios corresponding to certificates that show property rights inprivate law such as handprints, checks, carriage notes, cargocertificates, warehouse certificates, stock certificates, bondcertificates, tokens and deeds of mortgage.

FIG. 11A shows an example of a check 1301 attached with an ID chip 1302of the invention. Although the ID chip 1302 is attached to inside of thecheck 1301 in FIG. 11A, it may be provided on the surface of the checkand exposed.

FIG. 11B shows an example of a passport 1304 attached with an ID chip1303 of the invention. Although the ID chip 1303 is attached to thefront page of the passport 1304 in FIG. 11B, it may be attached toanother page of the passport.

FIG. 11C shows an example of a token 1306 attached with an ID chip 1305of the invention. The ID chip 1305 may be attached to either inside ofthe token 1306 or on the face thereof to be exposed.

The ID chips of the invention using integrated circuits with TFTs areinexpensive and thin, and hence, the ID chips are suitable toapplications in that the ID chips are eventually discarded by consumers.In particular, when the ID chips are applied to products in whichdifference in price in units of several yen to several tens yensignificantly affects sales, a packing material having the inexpensive,thin ID chip of the invention is very advantageous. The packing materialcorresponds to a support member which is formed to wrap up an objectsuch as a plastic wrap, a plastic bottle, a tray and a capsule.

A state of packing a boxed meal 1309 offered for sale by a packingmaterial 1308, which is attached with an ID chip of the invention, isdepicted in FIG. 12A. By storing price and the like of the product inthe ID chip 1307, the bill for the boxed meal can be settled in aregister having functions as a reader/writer.

For example, the ID chips of the invention may be attached to labels forgoods so that distribution process of the goods is managed.

As shown in FIG. 12B, an ID chip 1311 of the invention is attached to asupport medium such as a commercial product's label in that its rearface has viscosity. The label attached with the ID chip 1311 is pastedto a commercial product 1312. Identification information related to thecommercial product 1312 can be read wirelessly from the ID chip 1311attached to the label 1310. Accordingly, management of the commercialproduct becomes easier in the distribution process due to the ID chip1311.

In the case of using a nonvolatile memory as a memory for an integratedcircuit included in the ID chip 1311, distribution process of thecommercial product 1312 can be stored. Storage of the process in theproduction stage for goods can allow wholesalers, retailers andconsumers to grasp information about production areas, producers, datesof manufacture, processing methods and the like easily.

The present embodiment can be implemented by being freely combined withthe configurations of Embodiments 1 to 6.

Embodiment 8

The present embodiment will explain configurations of TFTs used for theID chips of the invention.

FIG. 13A shows a cross sectional view of TFTs according to theembodiment. Reference numeral 401 represents an n-channel TFT; and 402,a p-channel TFT. The configuration of the n-channel TFT 401 will beexplained as an example.

The n-channel TFT 401 comprises an active layer 405. The active layer405 includes two impurity regions 403 used as a source region and adrain region, a channel formation region 404 sandwiched between the twoimpurity regions 403, and two LDD (lightly doped drain) regions 410sandwiched between the impurity regions 403 and the channel formationregion. The n-channel TH 401 further comprises a gate insulating film406, a gate electrode 407, and two sidewalls 408 and 409 made frominsulating films.

Although the gate electrode 407 includes two-layer conductive films 407a and 407 b in the embodiment, the invention is not limited to theconfiguration. The gate electrode 407 may include a single-layerconductive film or two or more layer conductive films. The gateelectrode 407 overlaps with the channel formation region 404 of theactive layer 405 while sandwiching the gate insulating film 406therebetween. The sidewalls 408 and 409 overlap with the two LDD regions410 of the active layer 405 while sandwiching the gate insulating layer406 therebetween.

For example, the sidewalls 408 can be formed by etching a silicon oxidefilm with a thickness of 100 nm whereas the sidewalls 409 can be formedby etching an LTO film (a low temperature oxide film) with a thicknessof 200 nm. In the embodiment, the silicon oxide film used for thesidewalls 408 is formed by plasma CVD and the LTO film used for thesidewalls 409 is formed by reduced pressure CVD. Note that although thesilicon oxide film may contain nitrogen, the number of nitrogen atomsmust be set to be lower than that of oxygen atoms.

After doping an n-type impurity to the active layer 405 using the gateelectrode 407 as a mask, the sidewalls 408 and 409 are formed, and ann-type impurity element is doped to the active layer 405 utilizing thesidewalls 408 and 409 as masks so that the impurity regions 403 and theLDD regions 410 can be formed separately.

The p-channel TFT 402 has almost similar configuration to the n-channelTFT 401, however, a structure of an active layer 411 of the p-channelTFT 402 is only different of that for the n-channel TFT. The activelayer 411 does not have an LDD region, and includes two impurity regions412 and a channel formation region 413 sandwiched between the impurityregions. The impurity regions 412 are doped with a p-type impurity.Although FIG. 13A illustrates an example in that the p-channel TFT 402does not have an LDD region, the present invention is not limited to theconfiguration. The p-channel TFT 402 may comprise an LDD region.

FIG. 13B shows a case wherein each TFT shown in FIG. 13A has one kind ofsidewalls. An n-channel TFT 421 and a p-channel TFT 422 as shown in FIG.13B comprise one kind of sidewalls 428 and one kind of sidewalls 429,respectively. Each sidewall can, for example, be made by etching asilicon oxide film with a thickness of 100 nm. In the embodiment, thesilicon oxide film used for the sidewall 428 is formed by plasma CVD.The silicon oxide film may contain nitrogen, however, the number ofnitrogen atoms must be set to be lower than that of oxygen atoms.

FIG. 13C shows an example in which the sidewalls are formed afteretching the gate insulating films while utilizing the gate electrode asa mask with respect to the TFTs shown in FIG. 13B. An n-channel TFT 431and a p-channel TFT 432 as shown in FIG. 13C include gate electrodes433, 434 and gate insulating films 435, 436, respectively. The gateinsulating films 435 and 436 are formed by etching while using the gateelectrodes 433 and 434 as masks.

The gate electrodes 433 and 434 include two-layer conductive films 433a, 433 b and two-layer conductive films 434 a, 434 b in the embodiment,however, the present invention is not limited to the configuration. Thegate electrodes 433 and 434 may be formed of single-layer conductivefilms or two or more layer conductive films.

FIG. 13D shows a configuration of bottom-gate TFTs. Reference numeral441 denotes an n-channel TFT; and 422, a p-channel TFT. The n-channelTFT 441 will be explained in detail as an example.

In FIG. 13D, the n-channel TFT 441 comprises an active layer 445. Theactive layer 445 includes two impurity regions 443 used as a sourceregion and a drain region, a channel formation region 444 sandwichedbetween the impurity regions 443, and two LDD (lightly doped drain)regions 450 sandwiched between the two impurity regions 443 and thechannel formation region 444. The n-channel TFT 441 further includes agate insulating film 446, a gate electrode 447 and a protective film 448made from an insulating film.

The gate electrode 447 overlaps with the channel formation region 444 ofthe active layer 445 while sandwiching the gate insulating film 446therebetween. The gate insulating film 446 is formed after forming thegate electrode 447 and the active layer 445 is formed after forming thegate insulating film 446. The protective film 448 overlaps with the gateinsulating film 446 while sandwiching the channel formation region 444therebetween.

The protective film 448, for example, can be formed by etching a siliconoxide film with a thickness of 100 nm. In the embodiment, the siliconoxide film is formed by plasma CVD as the protective film 448. Note thatthe silicon oxide film may contain nitrogen, however, the number ofnitrogen atoms must be set to be lower than that of oxygen atoms.

After doping an n-type impurity to the active layer 445 utilizing a maskmade from a resist, the protective film 448 is formed, and an n-typeimpurity is doped to the active layer 445 while utilizing the protectivefilm 448 as a mask so that the impurity regions 443 and the LDD regions450 can be formed separately.

Although the p-channel TFT 442 has a almost similar structure to then-channel TFT 441, the structure of the active layer 451 of thep-channel TFT 442 is only different from that of the n-channel TFT. Theactive layer 451 does not include an LDD region, and includes twoimpurity regions 452 and a channel formation region 453 sandwichedbetween the two impurity regions 452. The impurity regions 452 are dopedwith a p-type impurity. Although FIG. 13A shows the example in which thep-channel TFT 442 does not have an LDD region, the invention is notlimited to the configuration. The p-channel TFT 442 may comprise an LDDregion.

This embodiment can be implemented by being freely combined with theconfigurations in Embodiments 1 to 7.

1. A semiconductor device comprising: a first flexible substrate; afirst sealing film over the first flexible substrate; an integratedcircuit comprising a transistor over the first sealing film; an antennaover the first sealing film, the antenna being configured to receive asignal from a reader/writer wirelessly and being electrically connectedto the integrated circuit; a second sealing film over the integratedcircuit and the antenna wherein the integrated circuit and the antennaare interposed between the first sealing film and the second sealingfilm; and a second flexible substrate over the second sealing film;wherein each of the first sealing film includes at least two inorganicinsulating films and an organic insulating film interposed between thetwo inorganic insulating films.
 2. The semiconductor device according toclaim 1 wherein the transistor is a thin film transistor.
 3. Thesemiconductor device according to claim 1 wherein each of the twoinorganic insulating films comprises a material selected from the groupconsisting of silicon nitride, silicon nitride oxide, aluminum oxide,aluminum nitride, aluminum nitride oxide or aluminum silicon nitrideoxide.
 4. The semiconductor device according to claim 1 wherein theorganic insulating film comprises a material selected from the groupconsisting of polyimide, acrylic, polyamide, polyimide amide,benzocyclobutene or epoxy resin.